QUOTE (Arnold B. Krueger @ Jan 21 2013, 14:48) <{POST_SNAPBACK}>
The above seems to makes no sense. When receiving SP/DIF there is and can be no source of clocking information other than the input data stream. The clock that is used to decode the input data stream must be sample-aligned with the input data and therefore synchronized with it.
Right. Yet there are cards which can be switched to internal clock, while capturing data from the SPDIF receiver. Such as most Envy24-based ones. Of course it is not a correct mode of operation since as you say the incoming I2S data from the SPDIF receiver are not aligned with the internal clock and data corruption occurs. Actually they can be, provided the SPDIF output provides master clock for the whole chain (sort of SPDIF loopback).
QUOTE
External clocking does not usually affect the reception of input SP/DIF data streams. External clocking geneally affects only the output data stream which may be clocked by an internal or external clock. Often there is an option for the output clock to be synchronized with the input data stream.
That would require the output part to use a different clock from the input part. I know that is not the case for Envy24, perhaps USB-based controllers are separated in that way. To find out is a nice project for a few evenings, maybe one day when I have nothing else to do... :-)